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Integrated Circuit Systems, Inc.
ICS9248-96
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E type chipset. Output Features: * 2- CPUs @ 2.5V, up to 166.5MHz. * 9 - SDRAM @ 3.3V, up to 155MHz including 1 free running * 8 - PCICLK @ 3.3V * 1 - IOAPIC @ 2.5V, * 2 - 3V66MHz @ 3.3V, 2X PCI MHz * 2 - 48MHz, @ 3.3V fixed. * 1 - 24/48MHz, @3.3V selectable by I2C * 1 - REF @v3.3V, 14.318MHz. Features: * Up to 166.5MHz frequency support * Support FS0-FS3 strapping status bit for I2C read back. * Support power management: Through Power down Mode from I2C programming. * Spread spectrum for EMI control ( 0.25% center). * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: < 250ps * 3V66 - 3V66: <175ps * PCI - PCI: <500ps * CPU-SDRAM<500ps * For group skew specifications, please refer to group timing relationship table.
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD. ** 60K pull-up to VDD on indicated input 1 These are double strength.
Block Diagram
Functionality
FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) 3V66 (MHz) PCICLK (MHz) I OA P I C
1=PCICLK/2
I OA P I C
0=PCICLK
(MHz)
(MHz)
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
66.80 68.00 100.30 103.00 133.73 145.00 133.73 137.33 140.00 140.00 118.00 124.00 133.70 137.00 150.00 72.50
100.20 102.00 100.30 103.00 100.30 108.75 100.30 103.00 105.00 140.00 118.00 124.00 133.70 137.00 112.50 108.75
66.80 68.00 66.87 68.67 66.87 72.50 66.87 68.67 70.00 93.33 78.67 82.67 89.13 91.33 75.00 72.50
33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25
16.70 17.00 16.72 17.17 16.72 18.13 16.72 17.17 17.50 23.33 19.67 20.67 22.28 22.83 18.75 18.13
33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25
Additional frequencies programming.
selectable
through
I2C
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ICS9248-96
General Description
ICS9248-96 is the single chip clock solution for designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 2 C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS924896 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
GNDREF, VDDREF = REF0, X1, X2 GNDPCI , VDDPCI = PCICLK [9:0] GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F, supply for PLL core GND3V66 , VDD3V66 = 3V66 GND48 , VDD48 = 48MHz, 24_48MHz, VDDLAPIC = IOAPIC GNDLCPU , VDDLCPU = CPUCLK [1:0]
Pin Configuration
PIN NUMBER 1 2, 9, 10, 18, 25, 30, 38 3 4 5, 6, 14, 21, 29, 34, 42 8, 7 11 12 PIN NAME FREQ_IOAPIC REF0 VDD X1 X2 GND 3V66 [1:0] FS0 PCICLK0 FS1 PCICLK1 SEL24_48MHz# PCICLK2 PCICLK [7:3] PD# SCLK SDATA FS3 48MHz_0 48MHz_1 TYPE IN OUT PWR IN OUT PWR OUT IN OUT IN OUT IN OUT OUT IN IN IN IN OUT OUT IN DESCRIPTION If FREQ_APIC = 0, APIC Clock = PCICLK If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default) 14.318 MHz reference clock. 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Ground pin for 3V outputs. 3.3V Clocks Frequency select pin. PCI clock output Frequency select pin. PCI clock output Logic inputs frequency select I/O/USB output, When a "0" is latched, output frequency = 48MHz When a "1" is latched, output frequency = 24MHz PCI clock output PCI clock outputs. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock input of I2C input, 5V tolerant input Data input for I2C serial input, 5V tolerant input Frequency select pin. 48MHz output clocks 48MHz output clocks Frequency select pin.
13 20, 19, 17, 16, 15
22 23 24
26 27 28 31
FS2 24_48MHz
SDRAM_F
OUT
OUT OUT PWR OUT PWR OUT PWR
24 or 48MHz output
Free running SDRAM - used for feed back to chipset, should remain on always. SDRAM clock outputs Ground pin for the CPU clocks. CPU clock outputs. Power pin for the CPUCLKs. 2.5V 2.5V clock output Power pin for the IOAPIC. 2.5V
32, 33, 35, 36, 37, SDRAM [7:0] 39, 40, 41, 43 GNDLCPU 44, 45 CPUCLK [1:0] 46 VDDLCPU 47 IOAPIC 48
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VDDLAPIC
2
ICS9248-96
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-96
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit (2, 7:4) CPUCLK (MHz) SDRAM (MHz) Description 3V66 (MHz) PCICLK (MHz) 33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25 37.50 13.83 36.67 40.00 41.67 34.63 35.00 38.33 48.33 33.25 50.00 33.25 51.67 55.50 38.33 33.25 FREQ_IOAPIC (MHz) 1 0 16.70 33.40 17.00 34.00 16.72 33.43 17.17 34.33 16.72 33.43 18.13 36.25 16.72 33.43 17.17 34.33 17.50 35.00 23.33 46.67 19.67 39.33 20.67 41.33 22.28 44.57 22.83 45.67 18.75 37.50 18.13 36.25 18.75 37.50 6.92 13.83 18.33 36.67 20.00 40.00 20.83 41.67 17.31 34.63 17.50 35.00 19.17 38.33 24.17 48.33 16.63 33.25 25.00 50.00 16.63 33.25 25.83 51.67 27.75 55.50 19.17 38.33 16.63 33.25 Spread Precentage +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center* +/- 0.25% Center* +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center* PWD
0 0 0 0 0 66.80 100.20 66.80 0 0 0 0 1 68.00 102.00 68.00 0 0 0 1 0 100.30 100.30 66.87 0 0 0 1 1 103.00 103.00 68.67 0 0 1 0 0 133.73 100.30 66.87 0 0 1 0 1 145.00 108.75 72.50 0 0 1 1 0 133.73 100.30 66.87 0 0 1 1 1 137.33 103.00 68.67 0 1 0 0 0 140.00 105.00 70.00 0 1 0 0 1 140.00 140.00 93.33 0 1 0 1 0 118.00 118.00 78.67 0 1 0 1 1 124.00 124.00 82.67 0 1 1 0 0 133.70 133.70 89.13 0 1 1 0 1 137.00 137.00 91.33 Bit 2, 0 1 1 1 0 150.00 112.50 75.00 Bit 7:4 0 1 1 1 1 72.50 108.75 72.50 1 0 0 0 0 75.00 112.50 75.00 1 0 0 0 1 83.00 83.00 27.67 1 0 0 1 0 110.00 110.00 73.33 1 0 0 1 1 120.00 120.00 80.00 1 0 1 0 0 125.00 125.00 83.33 1 0 1 0 1 69.25 103.88 69.25 1 0 1 1 0 70.00 105.00 70.00 1 0 1 1 1 76.67 115.00 76.67 1 1 0 0 0 145.00 145.00 96.67 1 1 0 0 1 66.50 99.75 66.50 1 1 0 1 0 150.00 150.00 100.00 1 1 0 1 1 99.75 99.75 66.50 1 1 1 0 0 155.00 155.00 103.33 1 1 1 0 1 166.50 166.50 111.00 1 1 1 1 0 153.33 115.00 76.67 1 1 1 1 1 133.00 99.75 66.50 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 2, 7:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0.25% Center Spread 0 - Running Bit 0 1- Tristate all outputs
00011 Note1
0 1 0
Note 1: Default at power-up will be for latched logic inputs to define frequency (Bit 3 = 0). * These frequencies with spread enabled are equal to original Intel defined frequencies with -0.5% down spread.
I2C is a trademark of Philips Corporation
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ICS9248-96
Byte 1: Control Register (1= enable, 0 = disable)
Byte 2: SDRAM, Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 28 27 26 31
PWD X X X X 1 1 1 1
DESCRIPTION FS3# FS0# FS2# 24_48MHz, 0 = 24MHz 48MHz_1 48MHz_0 ( R e s e r ve d ) SDRAM_F
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 32 33 35 36 37 39 40 41
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 3: PCI, Control Register (1= enable, 0 = disable)
Byte 4: Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 20 19 17 16 15 13 12 11
PWD 1 1 1 1 1 1 1 1
DESCRIPTION PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 8 7 47 44 45
PWD 1 1 1 X 1 X 1 1
DESCRIPTION ( R e s e r ve d ) 3V66_1 3V66_0 FREQ_IOAPIC# IOAPIC FS1# CPUCLK1 CPUCLK0
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes:
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
1. Disable means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Note: Don't write into this register. Writing into this register can cause malfunction
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ICS9248-96
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS924896 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, then only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Fig. 1
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ICS9248-96
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low, all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 ms. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-96
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table
Group CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to PCI USB & DOT CPU 66MHz Offset 2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Async Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Async Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Async Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL VIN = VDD Input High Current IIH VIN = 0 V; Inputs with no pull-up resistors IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors IIL2 IDD3.3OP CL = Max loads; CPU @ 66 MHz; SDRAM @ 100 MHz IDD2.5OP IDD3.3OP Operating Supply CL = Max loads; CPU @ 100 MHz; SDRAM @ 100 MHz Current IDD2.5OP IDD3.3OP CL = Max loads; CPU @ 133 MHz; SDRAM @ 133 MHz IDD2.5OP Power Down Supply Current Input Frequency Input Capacitance1 Transition time Settling time1 Clk Stabilization1
1
MIN 2 VSS - 0.3 -5 -5 -200
TYP
MAX VDD + 0.3 0.8 5
UNITS V V mA mA
300 12 300 25 300 35 300 14.31818
340 15 350 30 420 40 600
mA mA mA A MHz pF pF pF ms ms ms
IDD3.3PD Fi CIN COUT CINX Ttrans Ts TSTAB
CL = Max loads; VIN = VDD or GND VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency
27
1
5 6 45 3 3 3
Guaranteed by design, not 100% tested in production.
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ICS9248-96
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 RDSP2B VO = VDD/2 Output Impedance VOH2B IOH = -1 mA Output High Voltage IOL = 1 mA VOL2B Output Low Voltage VOH = 1.0 V IOH Output High Current VOH = 2.375 V VOL = 1.2 V IOL Output Low Current VOL = 0.3 V 1 tr 0.4 V to 2.0 V Rise Time tf 2.0 V to 0.4 V Fall Time1 1 dt VT = 1.25 V Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
MIN 13.5 2
-27 27 0.5 0.5 45
TYP 14 2.5 0.2 -85 -9 68 20 1.1 1.1 50 50 200
MAX 45 0.4 -27
UNITS V V mA mA ns ns % ps ps
30 2 2 55 175 250
tsk tjcyc-cyc
VT = 1.25 V VT = 1.25 V; 66 MHz < fCPU < 133 MHz fSDRAMb= 100 MHz or 133 MHz Spread ON or OFF
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance VO = VDD/2 RDSP1B Output High Voltage VOH1 IOH = -1 mA Output Low Voltage VOL1 IOL = 1 mA VOH = 1.0 V IOH1 Output High Current VOH = 3.135 V VOL = 1.95 V IOL1 Output Low Current VOL = 0.4 V Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V 1 dt1 VT = 1.5 V Duty Cycle 1 Skew window tsk1 VT = 1.5 V Jitter, Cycle-to-cycle1 tjcyc-cyc1 VT = 1.5 V
1
MIN 12 2.4
-33 30 0.5 0.5 45
TYP 18 3.3 0.1 -136 -13 115 28 1.2 1.3 53.6 37 280
MAX 55 0.4 -33
UNITS V V mA mA ns ns % ps ps
38 2 2 55 175 500
Guaranteed by design and characterization, not 100% tested in production.
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ICS9248-96
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 RDSP2B VO = VDD/2 Output Impedance VOH2B IOH = -1 mA Output High Voltage VOL2B IOL = 1 mA Output Low Voltage VOH = 1.0 V IOH Output High Current VOH = 2.375 V VOL = 1.2 V IOL Output Low Current VOL = 0.3 V 1 tr 0.4 V to 2.0 V Rise Time tf 2.0 V to 0.4 V Fall Time1 1 dt VT = 1.25 V Duty Cycle 1 Jitter, Cycle-to-cycle tjcyc-cyc4B VT = 1.25 V
1
MIN 13.5 2 -27 27 0.5 0.5 45
TYP 14 2.5 0.2 -9 68 20 1.1 1.1 50 130
MAX 45 0.4 -27 30 2 2 55 500
UNITS V V mA mA ns ns % ps
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance VO = VDD/2 RDSP3 Output High Voltage VOH3 IOH = -1 mA IOL = 1 mA Output Low Voltage VOL3 VOH = 2.0 V IOH3 Output High Current VOH = 3.135 V VOL = 1.0 V IOL3 Output Low Current VOL = 0.4 V Rise Time1 tr3 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf3 VOH = 2.4 V, VOL = 0.4 V 1 dt3 VT = 1.5 V Duty Cycle 1 Skew window tsk3 VT = 1.5 V Jitter1 tjcyc-cyc VT = 1.5 V
1
MIN 10 2.4 -54 54 0.4 0.4 45
TYP 3.3 0.01 -124 -20 105 46 1 1 53 98 170
MAX 24 0.4 -46 53 1.6 1.6 55 250 250
UNITS V V mA mA ns ns % ps ps
Guaranteed by design and characterization, not 100% tested in production.
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ICS9248-96
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance1 VO = VDD/2 RDSP1B Output High Voltage VOH1 IOH = -1 mA Output Low Voltage VOL1 IOL = 1 mA VOH = 1.0 V IOH1 Output High Current VOH = 3.135 V VOL = 1.95 V IOL1 Output Low Current VOL = 0.4 V Rise Time1 tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V 1 dt1 VT = 1.5 V Duty Cycle Skew window1 tsk1 VT = 1.5 V Jitter, Cycle-to-cycle1 tjcyc-cyc1 VT = 1.5 V
1
MIN 11 2.4 -33 30 0.5 0.5 45
TYP 25 3.2 0.1 -136 -13 115 38 1.3 1.6 51.6 330 145
MAX 55 0.55 -33 38 2 2 55 500 500
UNITS V V mA mA ns ns % ps ps
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance VO = VDD/2 RDSP5 Output High Voltage VOH5 IOH = -1 mA Output Low Voltage VOL5 IOL = 1 mA VOH = 1.0 V IOH5 Output High Current VOH = 3.135 V VOL = 1.95 V IOL5 Output Low Current VOL = 0.4 V Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf5 VOH = 2.4 V, VOL = 0.4 V 1 dt5 VT = 1.5 V Duty Cycle VT = 1.5 V; 48MHz tjcyc-cyc5 Jitter, Cycle-to-cycle1 VT = 1.5 V; REF
1
MIN 20 2.4 -29 29 1 1 45
TYP 22 3.2 0.1 -136 -13 115 1.2 1.2 53 200 780
MAX 60 0.4 -23 27 4 4 55 500 1000
UNITS V V mA mA ns ns % ps ps
Guaranteed by design and characterization, not 100% tested in production.
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ICS9248-96
N
c
SYMBOL
300 mil SSOP In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
L
INDEX AREA
E1
E
12 D h x 45
A A1 b c D E E1 e h L N a VARIATIONS N 48
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
A A1
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
-Ce
b SEATING PLANE .10 (.004) C
Ordering Information
ICS9248yF-96LF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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